1. Technical Field
The present invention relates in general to improved data processing systems and in particular to a method and system for enhanced processing efficiency within a data processing system. Still more particularly, the present invention relates to an improved method and system for nonsequential processing of an ordered sequence of scalar and vector instructions within a data processing system.
2. Description of the Related Art
In known data processing systems instructions are normally processed in a specific order which is specified by the program. Normally, these instructions are both executed and finished sequentially in this program order. To increase performance and limit delays, modern data processing systems have been enhanced to permit the finishing of program instructions in a nonsequential order, so as to overlap with execution instructions. However, execution instructions are generally limited to the sequential order required by the program. A general requirement for such program instruction overlap is that the instructions are completed as though they had been accomplished in the order specified by the program. Program instruction overlap is desirable to increase performance but may involve increased machine complexity and hardware costs. However, it is generally considered beneficial and typically enhances processing efficiency to permit instruction overlap which accomplishes both execution and finishing of program instructions in an out of order sequence.
High level data processing systems typically utilize two types of processing units, namely scalar processing units and vector processing units. Scalar processing units are designed to execute scalar instructions and vector processing units are designed to execute vector instructions. When utilized in conjunction within one data processing system there are generally two processing strategies for processing scalar and vector instructions which are currently proposed.
According to a first processing strategy, a mixed sequence or chain of instructions, which includes both scalar instructions and vector instructions, is decoded by a decoder for controlling execution of the individual instructions. A typical example of such a strategy is a system disclosed in an article by Richard M. Russell, entitled The CRAY-1 Computer System contained in communications of the ACM COMMUNICATIONS, January 1978.
A second processing strategy includes separate instruction decoders for decoding the scalar instructions and vector instructions. A typical system utilizing this strategy is discussed, for example, in an article entitled Hitachi Supercomputer S-810 Array Processor System, by T. Odaka et al., contained in Supercomputers, published by Elevier Science Publishers BV (North-Holland) 1986. In this system, instructions are decoded by two separate logical units. Utilizing the first processing strategy control over the two species of instructions is inclusive of the control for ensuring proper sequence established between the scalar instructions and the vector instruction may be realized in a facilitated manner, by virtue of the fact that the scalar instructions and vector instructions are intermixed.
Alternately, the second proposed processing strategy permits two types of instructions to be executed independently of each other, thereby facilitating parallel processing, because scalar instruction processing is separate from vector instruction processing. However, the independence of the scalar processing unit and the vector processing unit from each other requires that the vector processing unit be activated by the scalar processing unit. For activation of a vector processing unit, all variety of information required for initiating the vector processing must be established by the scalar processing unit. This establishment processing tends to involve an extended time for preparation before vector computation may be initiated, rendering it difficult or even impossible to make use of the functional performance specific to the vector processing unit for the computation of vectors of short vector length. Additionally, the second processing strategy requires circuitry for informing the scalar processing unit of the fact that a given processing of significance has been completed on the part of the vector processing unit at a given time.
In view of the above, it should be apparent that a need exists for a data processing system which may be utilized to execute an intermixed sequence of scalar and vector instructions in a nonsequential manner with a high degree of efficiency.